- All VLSI EDA tools licenses under SMDP Chip to System Design Project are received and installed.
- A MOU was signed by Director SGSITS, Indore, Director, CEERI Pilani and MIT, Government of India for Chip to System Design project running in E & I department.
8. ISTE -STTP (2 Week) on CMOS, Mixed Signal & Radio Frequency VLSI Design (30th Jan 2017 to 4th Feb 2017)
9. Vendor Training Program on Mentor Graphics (26th to 29th December 2016)
10. STC on Analog & Mixed signals System Design ( March 23-27 2015)