- AICTE Sponsored One Week Online STTP on “Mixed Signal & Radio Frequency VLSI Design” in 3 Phase Download File | IMG | 12KB |
- STTP-1 during 23rd to 28th Nov 2020 Download File | IMG | 32KB |
- STTP-2 during 07th to 12th Dec 2020 Download File | IMG | 54KB |
- STTP-3 during 12th to 19th Dec 2020 Download File | IMG | 24KB |
3. AICTE Sponsored One week STTP onDesign & Development of System on chipusing Low Power VLSI” from 25/11/2019 to 30/11/2019
4.
- Alumni Meet in the department on 24/12/2018 Download File | IMG | 54KB |
- Industrial Visit of UG Students on 19/12/2018 Download File | IMG | 33KB |
- Industrial Visit of PG Students on 18/12/2018 Download File | IMG | 34KB |
- Teacher's Day Celebration Download File | IMG | 89KB |
- All VLSI EDA tools licenses under SMDP Chip to System Design Project are received and installed.
- A MOU was signed by Director SGSITS, Indore, Director, CEERI Pilani and MIT, Government of India for Chip to System Design project running in E & I department.
6.Achievement award Batch 2014-18 Download File | IMG | 58KB |
7. STTP workshop Recent Trends in VLSI Design (9 to 13 April 2018) Download File | IMG | 68KB |
8. ISTE -STTP (2 Week) on CMOS, Mixed Signal & Radio Frequency VLSI Design (30th Jan 2017 to 4th Feb 2017)
9. Vendor Training Program on Mentor Graphics (26th to 29th December 2016)
10. STC on Analog & Mixed signals System Design ( March 23-27 2015)
