1) Chip to Startup Project (2022-2027) - Ongoing
This project was launched to train 85000 number of specialized man power over a period of 5 year in area of VLSI & Embedded System Design. Department recieved the grant under various heads like capital equipment, training, consumable etc. The cluster under IIT Indore consisting of SGSITS Indore, IET-DAVV Indore, IIT Jammu, ABV-IIITM Gwalior has signed an MOU with end user & collaborator "Shree Pacetronix Ltd" Pithampur to design & fabricate iPACE-CHIP , a Pacemaker.
Funding Agency: Ministry of Electronics & Information Technology (Meity) Goverment of India.
Chief Investigator: Dr P. P Bansod, Professor
Co-chief Investigator: Dr. Rajesh Khatri,Associate Professor, Dr. R.C Gujar, Associate Professor 
Grant Received: Rs.96 Lacs
Status: Ongoing 
Outcome(Expected): A Pacemaker (iPACE-CHIP) chip is expected to be tape-out & be commercialize as end-product by "Shree Pacetronix Ltd" Pithampur,Indore. This end-product will be designed under cluster of IIT Indore, SGSITS Indore, IET-DAVV Indore,  IIT Jammu, ABV-IIITM Gwalior.

2) SMDP-C2SD (2015-2021) -Completed
Department has received the letter from Department of Electronics and Information Technology (DeitY), Govt. of India regarding the launch of Special Man-Power Development Programme (SMDP-III) also called as Chip to System Design (C2SD) project. Under the C2SD project, a total of 60 Institute are participating. These Institutes which includes all IITs, NITs are divided into three categories called as Resource centres, Participating Institutes and New Participating Institutes. There are 10 Resource Centres, 30 Participating Institutes and 20 New Participating Institutes. Each participating institute New Participating Institute is attached to resource centre. Our institute is Participating Institute and attached to IIT Bombay. The Director of the institute has signed an MOU with the Department of Electronics and Information Technology (Deity), Govt. of India as per the norms for participating Institutes. The department will receive the grant from Deity for setting up VLSI-EDA lab, books, consumables, contingency, travel grant for presenting paper, attending workshops, conference and seminars. The role and responsibility of the department is to provide research facility to the student and to design and fabricate ICs of their research work under India Chip programme funded by Deity. It is also expected to start a Networked Ph.D. programme under this project. The other activities which includes under this project are to design ASCIs, Knowledge exchange programme.
Funding Agency: Ministry of Electronics & Information Technology (Meity) Goverment of India.
Chief Investigator: Dr. D.K Mishra, Professor
Co-chief Investigator: Dr. Rajesh Khatri, Associate Professor
Grant Recieved: Rs.1 crore 66 Lacs
Status: Completed
Outcome: 1) An SOC enlitted " A Versatile Physiological Signal Monitoring System for Healthcare" was tape-out as a cluster project under IIT Bombay, SVNIT Surat, IIT Gandhinagar & IIT Indore.
2) An ASIC enlitted "A 2.4 GHz Direct Conversion RF Reciever Front" was designed in UMC 180 nm 1P6M Technology & Simulated.  

3) SMDP-II (2005-2013) -Completed
This research project was funded by Ministry of Information and Communication Technology, Govt. of India. The aim of project was to generate man power in VLSI. Ministry provided funds for various activities like purchasing books, equipments, attending international/national conferences/workshop. Department have designed and fabricated an integrated chip of "A Two stage CMOS OP-AMP" under this project fund.
Funding Agency: Ministry of Electronics & Information Technology (Meity) Govement of India.
Chief Investigator: Dr. D.K Mishra, Professor
Co-chief Investigator: Mr. Pramod K. Jain , Associate Professor
Grant Recieved: Rs.55 Lacs
Status: Completed
Outcome: A chip enlitted "A Two Stage CMOS OP-AMP" was tape-out using UMC 180 nm 1P6M Technology.

4) R & D Project- Completed