Mr. D. S. Ajnar

  • Designation:  Associate Professor
  • Employee ID: 3300244
  • Qualification:  M.E.
  • Date of joining:  7/4/1995
  • : 091-731-2582422
  • : This email address is being protected from spambots. You need JavaScript enabled to view it.
  • : Detailed Profile
About Faculty: Research Interests: VLSI, ACTIVE FILTERS
Education and Qualification:

S. No.

Degree

Specialization

Year

University/Board

1

M.E.

Electronics (DTI)

2003

RGPV BHOPAL

2

B.E.

Electronics and Telecommunication

1993

DAVV
Work Experience:

S. No.

Designation

 Department

Employer  Name

Duration of Employment

1

Associate Professor/ Reader( PB-2)

Electronics & Instrumentation Engineering.

SGSITS Indore

21st April 2009 to Till Date

2

Associate Professor/ Reader( PB-1)

Electronics & Instrumentation Engineering.

SGSITS Indore

21st April 2006 to 20th April 2009

3

Senior Lecturer

Electronics & Instrumentation Engineering.

SGSITS Indore

21st April 2001 to 20th April 2006

4

Lecturer

Electronics & Instrumentation Engineering.

SGSITS Indore

7th  April 1995 to 20th April 2001
Research Details:
  • Mr. D.S. Ajnar is doing research in the field of Filter Design, simulation and Synthesis. He has Guided various research based projects to BE, and ME students and Actively involved in doing research since 1995.He  has published various research papers in the renowned journals and conferences.
Publications:

Research Paper Publications

(I)      International/National Journal Publications

 Design of 32 tap finite impulse response filter using Vedic multiplier and KoggeStone Adder International journal of recent technology and engineering. IJRTE ISSN 2277-3878 volume -8 issue-2 July 19 page no 6138-6141

(II)    International/National Conference Publications
  • .FPGA implementation of quantum comparator using reversible logic (springer international conference-ICSCT 2019)Hyderabad .India
  • .Design and Simulation of two stage sample and hold circuit with low power using current conveyor .4th international conference on communication and electronics systems, July 2019 Coimbatore. India IEEE sponsored
  • Neelesh Jain, D. S. Ajnar, P. K. Jain "Optimization of Advanced Encryption Standard Algorithm (AES) on Field Programmable Gate Array (FPGA)" in International Conference on Communication and Electronics Systems (ICCES) 2019
  • Vivek Kumar Jain, D. S. Ajnar, P. K. Jain"Design and Simulation of Two Stage Sample and Hold Circuit with Low Power using Current Controlled Conveyor" in International Conference on Communication and Electronics Systems (ICCES) 2019
  • DESIGN AND ANALYSIS OF NOISE IMMUNE HIGH SPEED  LEAKAGE TOLERANT SCHMITT TRIGGER USING 180 NM CMOS TECHNOLOGY in IEEE SPONSORED CONFERENCE MADRAS SECTION 2021
Other Details:

List of Conferences/Workshops/Seminars Organized

Advisory   committee   member   in    short   term   course   on    advancements   in microelectronics and VLSI design .sponsored by tequip-3 (11th-15th march 2019)

Dept. E&I ,sgsits indore

Invited Lectures/Expert Talks/Chairmanships at Conferences

GUEST SPEAKER (IETE CHEPTER) Designing analogue filter  8 August 2016,MIT Mandsaur